In an LSI such as an ASIC (Application Specific IC), there is a case when a memory such as an SRAM accessed by a functional block on the ASIC chip is implemented. It is often the case that a memory capacity can be made variable according to a system specification of a user in this kind of memory. A layout data of a memory having an arbitrary memory capacity specified by the user is generated by using a layout design tool such as a compiler. The memory (microcell) is automatically generated by inputting the arbitrary number of bits and the number of words into the compiler. The memory automatically generated by the compiler is called as a compiled memory or a compiled.
In general, in the memory such as the SRAM, as the number of memory cells coupled to bit lines transmitting data signals is large, load capacitance and wiring delay of the bit lines increase, and an access time becomes long. Japanese laid-open Patent Publication No. 2006-32577 describes a method in which the bit line includes a local bit line and a global bit line (hierarchical bit line structure) is proposed so as to decrease the number of the memory cells coupled to the bit line and to shorten the access time. In this case, the local bit line is wired in a memory cell array and to be directly coupled to the memory cells. The global bit line is coupled to the local bit line on the memory cell array, and coupled to a data input/output circuit.